//发送数据模块
module trans_data (
    input                       rst,
    input                       clk_10M,
    input                       clk_100M,
    input           [9:0]       tx_data,
    output                      tx_out
);

wire                            tx_in;
reg                 [9:0]       tx_dra;             //tx_data_ra
reg                 [9:0]       tx_drb;             //tx_data_rb;
reg                 [9:0]       tx_dr;
reg                             tx_dr_en;
reg                 [9:0]       tx_sft;             //tx shift
reg                 [3:0]       sft_count;

assign tx_in = tx_sft[9];

always @ (posedge clk_100M or posedge rst) begin
    if (rst) begin
        tx_dra <= 0;
        tx_drb <= 0;
    end
    else begin
        tx_dra <= tx_data;
        tx_drb <= tx_dra;
        tx_dr_en <= 1'b0;
        if (tx_dra != tx_drb) begin
            tx_dr <= tx_data;
            tx_dr_en <= 1'b1;
        end
    end
end

always @ (posedge clk_100M or posedge rst) begin
    if (rst) begin
        tx_sft      <= 0;
        sft_count   <= 0;
    end
    else begin
        if (tx_dr_en) begin
            tx_sft      <= tx_dr;
            sft_count   <= 0;
        end
        else if (sft_count == 9) begin
            tx_sft      <= tx_dr;
            sft_count   <= 0;
        end
        else begin
            tx_sft      <= {tx_sft[8:0],tx_sft[9]};
            sft_count   <= sft_count + 1;
        end
    end
end

lvds_tx lvds_tx_inst (
    .tx_in                  (tx_in),
    .tx_out                 (tx_out)
);

endmodule
